Stable, tunable, frequency sources or clocks are required for a number of different systems and applications. One well-known arrangement for such a frequency source is a phase-locked loop (PLL) with locks a voltage-controlled oscillator (VCO) to a stable reference frequency provided by a reference source such a crystal oscillator (XO), or a temperature compensated crystal oscillator (TCXO), etc.
FIG. 1 illustrates on example configuration of a basic PLL 100. PLL 100 includes a VCO 110, PLL feedback divider(s) 120, a phase detector or comparator 130, and a loop filter 140.
In operation, VCO 110 outputs a VCO output signal 115 having a frequency FVCO, a portion of which is provided to PLL feedback divider(s) 120—for example by means of a directional coupler or a power splitter (not shown in FIG. 1). PLL feedback divider(s) 120 divides the frequency of VCO output signal 115 by a PLL feedback divider ratio N, which may be a fixed, or a programmable value, and provides a feedback signal 125 at frequency FVCO/N to phase detector 130. A reference signal 135 is also provided to phase detector 130. Reference signal 135 may be obtained, for example, by dividing the frequency FCLK of an output signal 155 of a reference oscillator 150 (e.g., an XO or TCXO) by a fixed or programmable reference divider value M using reference divider 160. In that case, reference signal 135 has a reference frequency FREF=FCLK/M. Phase detector 130 compares feedback signal 125 to reference signal 135 and outputs a phase detection output signal 145 representing a phase difference between feedback signal 125 and reference signal 135. Loop filter 140 filters phase detection output signal 145 to produce a control signal or tuning voltage 155 which is applied to VCO 110 (e.g., to one or more varactors of VCO 110) to tune the frequency of VCO output signal 115. The operation of a basic PLL such as PLL 100 is well known and will not be repeated here in further detail.
Depending upon the particular application, there are various performance criteria for PLLs such as PLL 100 that can be important. One criterion which is typically important is jitter in the VCO output signal 115. Such jitter can be considered to include random jitter and deterministic jitter. In the frequency domain, random jitter manifests itself as phase noise on the sidebands or skirts on the spectrum of VCO output signal, and deterministic jitter manifests itself as spurious tones (often referred to as “frequency spurs”) on the sidebands or skirts on the spectrum of VCO output signal.
FIG. 2 illustrates an example of a frequency spectrum plot 200 of a VCO output signal from a PLL. Plot 200 illustrates a sharp peak 210 at the output frequency FVCO of the PLL. Phase noise 220 corresponds to random jitter in the VCO output signal, and frequency spurs 230 correspond to deterministic jitter.
In general, a primary source of deterministic jitter comprises spurious tones offset from the VCO central frequency, FVCO, at multiples or harmonics of the reference frequency FREF. These frequency spurs are often referred to as “reference spurs.”
Accordingly, to improve the overall jitter performance of a PLL, it is desired to reduce the levels of the reference spurs that appear on the VCO output signal's frequency spectrum sidebands.
FIG. 3 illustrates another example of a PLL 300. PLL 300 is similar to PLL 100, with the following significant differences. PLL 300 uses a digital phase/frequency detector (PFD) 330 and a charge pump 350 to provide the control signal for tuning and locking VCO 110 to the reference signal 135. The operation of PLLs with digital PFDs and charge pumps is well known and will not be repeated here. It is known that the PLL architectures that use a combination of digital PFD 330 and charge pump 350 can achieve very low reference spur levels when the up and down pulses of the charge pump are well matched to each other.
Meanwhile, it is well known that random jitter of a PLL output signal within the loop bandwidth of the PLL is dominated by a the jitter from the reference signal, multiplied by the PLL feedback divider ratio, N. Accordingly, to keep this random jitter low, it is necessary to keep the PLL feedback divider ratio N low (e.g., N=2, 4, 5, etc.). If it is required to operate the PLL at very high output frequencies (e.g., 20 GHz), and if N is kept small, then the phase detector must also operate at a high reference frequency, FREF. However, in general digital PFD circuits are limited in their frequencies of operation and, for example, cannot operate at frequencies of several GHz. So, for high output frequencies (e.g., several GHz), it is not possible to operate PLL 300 with low values for the PLL feedback divider ratio N (e.g., N=2, 4, 5, etc.). On the other hand, as explained above, if the PLL feedback divider ratio N is increased, then the level of random jitter in the VCO output signal is also increased.
What is needed, therefore, is a PLL which can operate at high frequencies with desired levels of both random and deterministic jitter.